Supply tracking clock multiplier

ABSTRACT

A circuit for and method of operating a supply tracking clock multiplier is provided. An embodiment of the present invention may permit a less power consuming portion of an integrated circuit to operate at a relatively higher average clock rate than a more power consuming portion operating at a relatively lower clock rate, by adjusting the duration of the cycles of the higher frequency clock. The adjustment may be according to the supply voltage changes that result from logic switching activity of the more power consuming portion, and may be performed in a manner that substantially matches the delay behavior of the logic. The phase of the higher frequency clock remains locked to the lower frequency clock. An embodiment of the present invention may reduce the area and cost of an integrated circuit by minimizing the need for other on-chip power supply noise mitigation approaches, while also improving device throughput and performance.

RELATED APPLICATIONS

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MICROFICHE/COPYRIGHT REFERENCE

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BACKGROUND OF THE INVENTION

In certain applications it is beneficial to run some parts of anintegrated circuit (IC) at a higher clock frequency than the majority ofthe chip. FIG. 1 illustrates an example of clock signals, clk1 x 110 andclk2 x 120, where clock signal clk2 x 120 is twice the frequency ofclock signal clk1 x 110. Examples of integrated circuits in whichportions of the device may operate at a higher frequency include, forexample, high performance microprocessors, digital signal processors(DSP), and IC's used for high speed data communications. To generate thehigher clock frequencies used in such applications, phase locked loops(PLLs) or delay locked loops (DLLs) may be used. The jitter performanceof these PLLs and DLLs is usually one of the key design parameters, andcustomarily the jitter is minimized to provide equal cycle times,independent of power supply noise. This is typically achieved by using aseparate power supply for the higher frequency clock circuitry, or byusing circuits having a propagation delay independent of the powersupply level.

In many IC devices, the on-chip power supply voltage has a pronouncedripple at the clock frequency of that portion of the device thatdominates the power dissipation. This ripple is caused by the clockcontrolled periodic supply current, which passes through on-chipresistive supply networks, and through the package inductances. Theripple results in a lower than average power supply voltage (i.e., adroop region), during the times when the logic consumes its peakcurrent. The IC circuitry may then experience some inductive overshoot(i.e., an overshoot region) above the average power supply voltage, whenthe instantaneous current consumed by the logic tapers off. In an edgetriggered design, the droop region usually appears close to the risingclock edge, when the majority of the device logic comprisesrising-edge-triggered flip-flops.

The propagation delay of logic gates in an IC is a function of the powersupply voltage at the time when the circuit evaluates. Higher powersupply voltages reduce propagation delay, lower supply voltages resultin increased propagation delay.

When one portion of an integrated circuit operates at a higher frequency(e.g. twice the frequency) than another portion that consumes themajority of the power, the higher frequency block is forced to operatein the droop region of the power supply ripple caused by the portion ofthe circuit that consumes the largest amount of power. FIG. 2illustrates the outline of an IC 210 comprising a smaller portion 230that may operate using a higher speed clock than the portion 220 of theIC 210 that consumes the majority of the power. Such a situationtypically forces an IC designer to limit the operating speed of higherspeed portion 230 of the IC 210 based upon logic propagation delaysavailable at the lower, droop region power supply voltages caused by thelarge power consuming portion 220, or to incorporate separate sources ofpower or additional noise reduction circuitry to minimize power supplynoise. The minimum power supply voltage in the droop region may besubstantially lower than the average supply level, impacting overalldevice performance, or the additional noise reduction measures may addcost to the device. This design problem can be expected to become moreand more pronounced as the device density of ICs increases, the powersupply voltages are scaled down, and power supply currents grow.

Further limitations and disadvantages of conventional and traditionalapproaches will become apparent to one of ordinary skill in the artthrough comparison of such systems with the present invention as setforth in the remainder of the present application with reference to thedrawings.

BRIEF SUMMARY OF THE INVENTION

Aspects of the present invention may be found in a clock multipliercircuit comprising a delay line circuit, a control circuit, and a mixercircuit. The clock multiplier circuit may be disposed on an integratedcircuit device having at least one other circuit comprising a pluralityof logic gates. In such an embodiment, the delay line circuit mayfunction to produce at each of a plurality of outputs, a delayed versionof a first clock signal, the delay of the delay line circuit beingdependent upon at least one control signal and a supply voltage. Thecontrol circuit may accept as inputs at least two of the plurality ofoutputs of the delay line circuit, and the control circuit may producethe at least one control signal. The control circuit may be adapted toadjust the at least one control signal in order to maintain apredetermined phase relationship of the at least two of the plurality ofoutputs of the delay line circuit. The mixer circuit may be adapted tocombine a subset of the plurality of outputs of the delay line circuitin order to produce a second clock signal having a number of cycles foreach cycle of the first clock signal. The clock multiplier circuit mayfunction to adjust a duration of one or more portions of the secondclock signal in response to the supply voltage while producing thenumber of cycles of the second clock signal during each cycle of thefirst clock signal and maintaining a predetermined timing relationshipof the first and second clock signals.

In an embodiment of the present invention, the delay line circuit mayhave four outputs, each output being a version of the first clock signalthat is delayed by an amount of time equal to a multiple of one fourththe period of the first clock signal. The control circuit may comprise aphase detector circuit for detecting a phase relationship between the atleast two of the outputs of the delay line circuit, the phase detectorproducing an output, and at least one filter for filtering the output ofthe phase detector, the at least one filter producing the at least onecontrol signal. The predetermined phase relationship of the at least twoof the plurality of outputs of the delay line circuit may comprise aphase difference of 360 degrees, and the number of cycles of the secondclock signal during each cycle of the first clock signal may be aninteger value of at least two. Delay characteristics of the delay linecircuit may be adapted to substantially match the delay characteristicsof the plurality of logic gates, with regard to changes in the supplyvoltage.

Further aspects of the present invention may be found in a systemcomprising at least one processor for processing data. The processor maycomprise a plurality of logic gates, a memory communicatively coupled tothe at least one processor, where the at least one processor has a clockmultiplier circuit. The clock multiplier circuit may comprise a delayline circuit that functions to produce a plurality of signals, eachsignal being a delayed version of a first clock signal, the amount ofdelay being dependent upon at least one control signal and a supplyvoltage. The clock multiplier circuit may also comprise a controlcircuit that accepts as inputs, at least two of the plurality ofsignals. The control circuit produces the at least one control signal,and is adapted to maintain a predetermined phase relationship of the atleast two of the plurality of signals by adjusting the at least onecontrol signal. In addition, the clock multiplier circuit may comprise amixer circuit adapted to combine a subset of the plurality of signals inorder to produce a second clock signal having a number of cycles foreach cycle of the first clock signal. The clock multiplier circuit mayfunction to adjust a duration of one or more portions of the secondclock signal in response to the supply voltage, while producing thenumber of cycles of the second clock signal during each cycle of thefirst clock signal and maintaining a predetermined timing relationshipof the first and second clock signals.

In an embodiment in accordance with the present invention, the controlcircuit may comprise a phase detector circuit for detecting a phaserelationship between the at least two of the plurality of signals, thephase detector producing an output, and at least one filter forfiltering the output of the phase detector, the at least one filterproducing the at least one control signal. The predetermined phaserelationship of the at least two of the plurality of signals maycomprise a phase difference of 360 degrees, and the number of cycles ofthe second clock signal during each cycle of the first clock signal maybe an integer value of at least two. Delay characteristics of the delayline circuit may be adapted to substantially match the delaycharacteristics of the plurality of logic gates, with regard to changesin the supply voltage.

Additional aspects of the present invention may be seen in a method ofmultiplying a first clock signal to produce a second clock signal. Sucha method may comprise receiving the first clock signal, delaying thefirst clock signal by a plurality of adjustable delays to produce aplurality of delayed signals, and determining a phase relationship oftwo of the plurality of delayed signals. The method may also comprisemodifying the plurality of adjustable delays based upon the phaserelationship and a supply voltage, if the phase relationship does notmeet a predetermined condition, and refraining from modifying theplurality of adjustable delays based upon the phase relationship and thesupply voltage, if the phase relationship meets the predeterminedcondition. In addition, the method may include generating a second clocksignal using at least two of the plurality of delayed signals. Each ofthe delayed signals may comprise a version of the first clock signalthat is delayed by an amount of time equal to an integer multiple of theperiod of the first clock signal divided by a predetermined integer. Thedetermining may comprise detecting the phase relationship of two of theplurality of delayed signals to produce phase relationship information,and filtering the phase relationship information.

In an embodiment of the present invention, the predetermined conditionmay comprise a phase difference of 360 degrees, and the number of cyclesof the second clock signal occurring during each cycle of the firstclock signal may be an integer value of at least two. At least one ofthe delaying and modifying may be adapted in order to substantiallymatch the delay characteristics of the plurality of adjustable delays tothe delay characteristics of a circuit receiving the second clocksignal, with regard to changes in the supply voltage.

Aspects of the present invention can also be found in an integratedcircuit comprising a first circuit portion that operates at a firstaverage clock rate and having a first power consumption, and a secondcircuit portion that operates at a second average clock rate and havinga second power consumption. The first average clock rate may be higherthan the second average clock rate, and the first power consumption maybe lower than the second power consumption. The first circuit portionmay operate according to a first clock, and a duration of cycles of thefirst clock may be adjusted. The duration of cycles of the first clockmay be adjusted in response to a supply voltage, and the duration ofcycles of the first clock may be adjusted to substantially match a delaycharacteristic of the second circuit portion. The second circuit portionmay operate according to a second clock, and the phase of the firstclock may be locked to the second clock.

These and other features and advantages of the present invention may beappreciated from a review of the following detailed description of thepresent invention, along with the accompanying figures in which likereference numerals refer to like parts throughout.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 illustrates an example of clock signals, clk1 x and clk2 x, whereclock signal clk2 x is twice the frequency of the clock signal clk1 x.

FIG. 2 illustrates the outline of an IC comprising a smaller portionthat may operate using a higher speed clock than the portion of the ICthat consumes the majority of the power.

FIG. 3 illustrates the current consumption of a simulated IC deviceduring logic switching using a system clock, clk1 x.

FIG. 4 illustrates worst case power supply voltage noise caused by thelarge and rapid changes in device supply current due to the simulated ICdevice power supply current changes shown in FIG. 3.

FIG. 5 illustrates a high level block diagram of a clock multipliercircuit, in accordance with an embodiment of the present invention.

FIG. 6 illustrates a block diagram of an exemplary clock multiplierdelay locked loop that may be a part of a clock multiplier circuit suchas the clock multiplier of FIG. 5, in accordance with an embodiment ofthe present invention.

FIG. 7 shows a block diagram illustrating an exemplary mixing circuitfor generating a higher frequency clock signal, clk2 x, from the outputsof the voltage controlled, supply-tracking delay line of FIG. 6, inaccordance with an embodiment of the present invention.

FIG. 8 illustrates clock signals phi1, phi2, phi3, phi4, that maycorrespond, for example, to clock signals phi1, phi2, phi3, and phi4 ofFIG. 7, respectively, along with clock signal clk1 x from which they arederived, in accordance with an embodiment of the present invention.

FIG. 9 shows a schematic of an exemplary basic delay element that may beused to implement, for example, the supply tracking delay elements ofFIG. 6, in accordance with an embodiment of the present invention.

FIG. 10 is a schematic diagram illustrating an exemplary embodiment of acharge pump that may be used to generate bias voltages, vbiasp andvbiasn, for the control of the basic delay elements of a voltagecontrolled, supply tracking delay line, such as basic delay element ofFIG. 9, in accordance with an embodiment of the present invention.

FIG. 11 shows a collection of signal waveforms from a simulation of anexemplary clock multiplier such as the clock multiplier of FIG. 5, inaccordance with an embodiment of the present invention.

FIG. 12 shows two graphs that illustrate how the even and odd clockcycle times of a supply tracking clock multiplier change with anincreasing power supply ripple amplitude delta between 0 and 100 mV, inaccordance with an embodiment of the present invention.

FIG. 13 shows a curve illustrating the dependency of the propagationdelay of a full adder in this process upon changes in the power supplyvoltage, Vdd, in accordance with an embodiment of the present invention.

FIG. 14 shows four curves illustrating the normalized performance duringeven and odd clock cycles, when both a supply tracking clock multiplierand a prior art clock multiplier are employed, respectively, inaccordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Aspects of the present invention address the problem of clockmultiplication in integrated circuits. More specifically, aspects of thepresent invention employ a delay locked loop (DLL) to create amultiplied clock signal where instead of designing for minimum jitter,the DLL is based upon delay elements that track as closely as possiblethe propagation delay sensitivity of the basic logic gates used in theIC caused by changes in the IC power supply. By using delay elementswith this property, a multiplied clock signal that provides increasedcomputation time when the supply droops may be generated. Although muchof the following discussion describes an embodiment of the presentinvention that doubles the frequency of a clock signal, this is not alimitation of the present invention. The arrangement described below maybe employed in the generation of other clock multiplication ratios,without departing from the spirit or scope of the present invention.

As described above, the switching of logic elements in an IC such as,for example, high performance processors, digital signal processors, andhigh speed data communication devices, may significantly affect powersupply voltages available to the logic elements of the device. To helpclarify this effect, FIG. 3 illustrates the current consumption of asimulated IC device during logic switching using a system clock, clk1 x.The illustration of FIG. 3 shows a rapid increase in supply current inregion 320 due to a rising edge of the system clock, clk1 x, followed bya smaller yet significant increase in supply current in region 330 dueto a falling edge of the system clock, clk1 x. These large and rapidchanges in IC supply current may be the source of significant powersupply noise depending upon, for example, power supply current pathresistances and inductances of bonds and lead wires.

FIG. 4 illustrates worst case power supply voltage noise caused by thelarge and rapid changes in device supply current due to the simulated ICdevice power supply current changes shown in FIG. 3. The illustration ofFIG. 4 shows a curve 410 of the simulated Vdd supply voltage, a curve430 of the simulated Vdd supply averaged over the 8 ns window of thesystem clock, a curve 440 of the simulated Vss supply voltage, a curve450 of the value of the simulated Vss supply averaged over the 8 nswindow of the system clock, and a curve 420 of the effective supplymeasured between the Vdd and Vss supplies. As shown in FIG. 4, theswitching activity of the simulated IC device generates an estimated 180mV peak-to-peak supply ripple that is mostly periodic with the systemclock, clk1 x. As can also be seen in the illustration of FIG. 4, onlyvery small power supply voltage fluctuations remain after the simulatedVdd and Vss supply voltages are averaged over an 8 ns clock cyclewindow.

FIG. 5 illustrates a high level block diagram of a clock multipliercircuit 500 in accordance with an embodiment of the present invention.The clock multiplier circuit 500 receives as its input a clock signal505 at a first frequency, and produces as its output a clock signal 595at a second frequency that is a multiple of the frequency of its inputclock signal 505. The circuit operates from power supply voltages Vdd510 and Vss 570 that are subject to electrical noise generated by othercircuitry sharing the Vdd 510 and Vss 570 power supplies. The clockmultiplier circuit 500 may be designed to provide a high speed clocksignal to a higher speed portion of an IC such as, for example, theportion 230 of IC 210 of FIG. 2.

FIG. 6 illustrates a block diagram of an exemplary clock multiplierdelay locked loop 600 that may be a part of a clock multiplier circuitsuch as the clock multiplier 500 of FIG. 5, in accordance with anembodiment of the present invention. As shown in FIG. 6, the delaylocked loop 600 comprises a voltage controlled, supply tracking delayline 620, a phase detector 640, a charge pump 650, and a loop filter660. The voltage controlled, supply-tracking delay line 620 comprisesfive supply tracking delay elements 621-625 connected in a sequentialfashion that create delayed versions of the input clock signal, clk1 x605. As shown in the illustration of FIG. 6, each of the supply trackingdelay elements 621-625 produces an output for use by other circuitry ofthe clock multiplier circuit, to be described in further detail below. Acontrol loop comprising the phase detector 630, the charge pump 640, andthe loop filter 650 is arranged to adjust the control voltage, vctrl660, so that the delay through four of the supply tracking delayelements 622-625, that is, between signal, phi1 626, and signal, phi5630, equals a phase delay of 360 degrees, i.e. one cycle of the incomingclock signal, clk1 x 605. The action of the control loop ensures thateach supply tracking delay element 622-625 contributes a 90 degreephase-shift between its input and its output, resulting in the outputsignals phi1 626, phi2 627, phi3 628, phi4 629 and phi5 630 of delayline 620 having a 90 degree phase separation. Although the illustrationof FIG. 6 relates to an embodiment of the present invention providing aclock multiplication ratio of 2, the voltage controlled, supply trackingdelay line 620 in various embodiments in accordance with the presentinvention may have different numbers of delay elements, each providingan equal amount of phase shift of the clock signal to be multiplied.Such embodiments may support generation of clock signals of a differentmultiple of the input clock signal from the example provided herein,without departing from the scope or spirit of the present invention.

FIG. 7 shows a block diagram illustrating an exemplary mixing circuit700 for generating a higher frequency clock signal, clk2 x 710, from theoutputs of the voltage controlled, supply-tracking delay line 620 ofFIG. 6, in accordance with an embodiment of the present invention. Themultiplied clock signal clk2 x 710 is generated by mixing two outputsignals, 180 degrees apart from each other, from the voltage controlled,supply-tracking delay line 620. As illustrated in FIG. 7, the mixingcircuit 700 uses four clock signals phi1 726, phi2 727, phi3 728, andphi4 729, which are separated by a phase delay of 90 degrees, one withrespect to the next. FIG. 8 illustrates clock signals phi1 826, phi2827, phi3 828, phi4 829, that may correspond, for example, to clocksignals phi1 726, phi2 727, phi3 728, and phi4 729 of FIG. 7,respectively, along with clock signal clk1 x 805 from which they arederived, in accordance with an embodiment of the present invention.Clock signals phi1 726, phi2 727, phi3 728, and phi4 729 of FIG. 7 mayalso correspond, for example, to the four clock signals phi1 626, phi2627, phi3 628, and phi4 629, respectively of FIG. 6.

The exemplary mixing circuit illustrated in FIG. 7 operates as follows,with additional reference to the timing diagram of FIG. 8. During theeven cycle 880 of FIG. 8, when clock signal phi2 727, 827 is low, andphi4 729, 829 is high, the transmission gate 760 passes the risingtransition of signal phi1 726, 826 to the input of the buffer 761 thatpasses the signal to the clk2 x output 710, 810. When clock signals phi2727, 827 and phi4 729, 829 change their polarity half a clock clk1 x 605cycle later, transmission gate 760 disconnects the clock signal phi1727, 827 from the input of buffer 761, and transmission gate 765connects the input of buffer 761 to clock signal phi3 728, 828. Thisresults in a falling clock edge at the input of buffer 761 that ispassed to the clk2 x output 710, 810. The odd cycle 885 of the clocksignal clk2 x 710, 810 then begins. After a quarter of a clock clk1 x605 cycle, clock signal phi3 728, 828 makes a transition from low tohigh, which is passed by transmission gate 765 to the input of buffer761, and to the clk2 x output 710, 810. After another quarter cycle ofthe clock clk1 x signal, phi2 727, 727 and phi4 729, 729 reversepolarity again, and phi1 726, 826 is passed by transmission gate 760 tothe input of buffer 761, resulting in a falling transition of the clocksignal clk2 x 710, 810. This sequence of events repeats for each cycleof the incoming clock signal clk1 x 605. Therefore, for each rising edgeof the clock signal clk1 x 605, two rising edges are created on theoutput clock signal clk2 x 710, 810.

FIG. 9 shows a schematic of an exemplary basic delay element 900 thatmay be used to implement, for example, the supply tracking delayelements 621-625 of FIG. 6, in accordance with an embodiment of thepresent invention. The basic delay element 900 comprises an inverterbuilt from NMOS transistor 901 and PMOS transistor 902. The pull-downcurrent of the inverter is controlled by bias voltage vbiasn 907 to thegate of NMOS transistor 903. NMOS transistor 904 with the gate connectedto Vdd provides a minimum current that corresponds to the maximumpull-down delay, if NMOS transistor 903 is shut off completely.Similarly, the pull-up current is controlled by bias voltage vbiasp 908,connected to the gate of PMOS transistor 905. PMOS transistor 906provides a minimum pull-up current, that corresponds to the maximumpull-up delay, when PMOS transistor 905 is shut off.

The NMOS transistor 904 and the PMOS transistor 906 guarantee that clockpulses are passed through the basic delay element 900, so that the clockedges needed for the control loop of FIG. 6 to function, are not lostwhen the bias voltages shut off the connected transistors.

The inverter comprising NMOS transistor 912 and PMOS transistor 913provides a decoupled and inverted output signal, o 911, that may be fedinto the phase detector of FIG. 6, or the mixer circuit of FIG. 7,without changing the stage delay of the basic delay element 900.

FIG. 10 is a schematic diagram illustrating an exemplary embodiment of acharge pump 1000 that may be used to generate bias voltages, vbiasp 1010and vbiasn 1009, for the control of the basic delay elements of avoltage controlled, supply tracking delay line, such as basic delayelement 900 of FIG. 9, in accordance with an embodiment of the presentinvention. The bias voltages vbiasp 1010 and vbiasn 1009 of FIG. 10 maycorrespond, for example, to the bias voltages vbiasp 908 and vbiasn 907of FIG. 9, respectively. In this example, a phase detector such as, forexample, the phase detector 640 of FIG. 6 may provide an active lowsignal, upb 1011, to raise bias voltage vbiasn 1009, and an active highsignal, dn 1012, to lower bias voltage vbiasn 1009. The bias voltage,vbiasn 1009, is lowered when signal, dn 1012, and signal, upb 1011, arehigh, i.e., when NMOS transistors 1001 and 1002 drain current from theloop capacitor implemented using PMOS transistor 1006. In the exemplaryembodiment of FIG. 10, a PMOS transistor 1006 is connected to V_(dd),thereby coupling supply noise from the V_(dd) power supply 1013 ontobias voltage, vbiasn 1009. This improves the delay tracking performanceof the supply tracking delay elements of a voltage controlled, supplytracking delay line, in an embodiment in accordance with the presentinvention. The PMOS transistors 1003 and 1004 raise bias voltage vbiasn1009, when signals, upb 1011, and, dn 1012, are both low.

The PMOS transistor 1005 provides a resetb input 1014, that may be usedto initialize the bias voltage vbiasn 1009 close to the level of the Vddpower supply 1013. This action may set the propagation delay of a supplytracking delay element such as, for example, the supply tracking delayelement 900 close to its lower delay bound.

The NMOS transistor 1007 converts the bias voltage vbiasn 1009 into acurrent, which is drawn through the diode-connected PMOS transistor1008. In an embodiment of the present invention, the voltage drop acrossthe PMOS transistor 1008 may be used as the bias voltage vbiasp 1010that controls the rising output edge propagation delay of the basicdelay element 900.

In an embodiment of the present invention, the supply tracking delayelements 621-625 of FIG. 6 may be constructed by appending a number ofbasic delay elements such as, for example, the basic delay element 900of FIG. 9. For example, in a clock multiplier that doubles the inputclock signal, each supply tracking delay element such as, for example,the supply tracking delay elements 621-625 of FIG. 6, may provide aquarter clock period of delay. The number of basic delay elements 900used to realize each supply tracking delay element 621-625 may becalculated by measuring the propagation delay of the basic delay element900 when device fabrication process conditions result in slow devices,the power supply voltage (i.e., V_(dd)−V_(ss)) available at the deviceis low, and the bias voltage, vbiasn 907, is close to the V_(dd) powersupply voltage. This set of conditions may be the operating point (i.e.,a slow chip and a low power supply voltage) when propagation delaytracking between the multiplied clock and the gates of the device ofinterest is most important. In this situation, vbiasp 1010 is lowbecause vbiasn 1009 is high. Therefore, the NMOS transistor 903 and thePMOS transistor 905 are on, and the propagation delay of the basic delayelement 900 most closely matches the propagation delay of logic gatescomprising stacks of two NMOS and two PMOS devices.

FIG. 11 shows a collection of signal waveforms from a simulation of anexemplary clock multiplier such as the clock multiplier 500 of FIG. 5,in accordance with an embodiment of the present invention. Thesimulation was performed assuming a 0.13 um complementarymetal-oxide-semiconductor (CMOS) process, Slow-slow CORNER, a powersupply voltage (shown by waveform 1105 of FIG. 11) of 1V with a rippleamplitude of delta=0.1V [V_(dd)=1.0V+0.1V*sin(2πf_(clk))], cycle timeT=1/f_(clk)=8 ns, temperature 125 deg C. The waveform 1101 illustratesthe bias voltage, vbiasn 907, used to control the NMOS transistors ofthe basic delay element 900 of FIG. 9. The waveform 1102 illustrates thebias voltage, vbiasp 908, used to control the PMOS transistors of thebasic delay element 900 of FIG. 9. The waveform 1103 shows a delayedversion of the input clock, clk1 x 110 of FIG. 1 or clk1 x 505 of FIG.5, with a 45 degree phase delay, and waveform 1104 shows a waveformtrailing the signal of waveform 1103 by 360 degree phase shift. Thesignals shown by waveforms 1103 and 1104 may correspond, for example, tothe input signals to the phase detector 640 of FIG. 6. The voltagecontrolled, supply tracking delay line in the exemplary embodiment ofthe simulation, which may correspond to the voltage controlled, supplytracking delay line 620 of FIG. 6, is adjusted to keep the phasedifference between these two signals at 360 degrees. The signal clk2 xshown by waveform 1106 is the multiplied (doubled) output clock, and maycorrespond to the multiplied clock signal clk2 x 595 of FIG. 5, or clk2x 710 of FIG. 7. It is clearly illustrated by the simulation resultsshown in FIG. 11 that the even clock cycle 1180 of the simulatedmultiplied clock signal clk2 x 1106 coinciding with the overshoot of thepower supply voltage waveform 1105, is significantly shorter than theodd clock cycle 1185 that coincides with the droop of the power supplyvoltage waveform 1105.

FIG. 12 shows two graphs that illustrate how the even 1280 and odd 1285clock cycle times of a supply tracking clock multiplier change with anincreasing power supply ripple amplitude delta between 0 and 100 mV, inaccordance with an embodiment of the present invention. The change inclock cycle time is approximately linear with the ripple amplitude deltaof the power supply voltage. In the illustration of FIG. 12, theduration of the even cycles decreases, and the duration of the oddcycles increases by a similar amount, so that the sum of two consecutivecycles of the multiplied clock, clk2 x, equals the period of theincoming clock, clk1 x. It should be noted that although theillustration of FIG. 12 illustrates the behavior of an embodiment of asupply tracking clock multiplier providing a multiplication ratio of 2,the present invention is not limited to use in clock multipliersproviding only a clock multiplication ratio of 2, and may be employedwith other clock multiplication ratios, without departing from thespirit or scope of the present invention.

FIG. 13 shows a curve 1310 illustrating the dependency of thepropagation delay of a full adder in this process upon changes in thepower supply voltage, Vdd. The propagation delay can be very accuratelydescribed by an equation, propagation delay=D/(Vdd−Vt)^(α), whereD=3.14×10⁻¹⁰, α=0.847, and Vt=0.539.

FIG. 14 shows four curves 1401, 1402, 1403, 1404 illustrating thenormalized performance during even and odd clock cycles, when both asupply tracking clock multiplier and a prior art clock multiplier areemployed, respectively, in accordance with an embodiment of the presentinvention. The curves shown in FIG. 14 were calculated by normalizingthe number of gate delays that fit into the odd and even cycle time ofthe multiplied clock, clk2 x. For this comparison the supply dependentinstantaneous computation speed was modeled asvlogic=1/delay=(Vdd−Vt)^(α)/D. By integrating vlogic over the respectiveclock cycle, the number of gates that can evaluate during that cycle maybe obtained. If an ideal, jitter free, clk2 x is used, the performancein the even cycle increases as shown by curve 1403, when the supplyripple increases, and the performance in the odd cycles decreases asshown by curve 1404, as the average supply during odd cycles drops dueto the supply droop. Assuming a supply ripple amplitude of 100 mV, theperformance during the odd cycles of a clock multiplier according to theprior art drops by approximately 12%. This is a significant degradation,indicating a pronounced supply ripple dependency of the clk2 x logic inthe presence of heavy clk1 x switching activity. When the doubled clock,clk2 x, is generated using a supply tracking DLL in accordance with thepresent invention, the performance during the even and odd cycles ofclk2 x, shown by curves 1401 and 1402, respectively, changes by lessthan 2%, thanks to the cycle width modulation of the supply trackingclock multiplier.

The prior art clock multiplying DLLs attempt to minimize the jitter ofthe multiplied clock, by using isolated supplies, or by using delayelements that show as little supply dependency as possible (differentialcurrent mode delay elements). An embodiment in accordance with thepresent invention may use delay elements that track the supply/delayperformance of logic gates, in order to provide longer execution timewhen the supply voltage drops. This is accomplished by shortening clockcycles at times when the supply is higher than average. The supplyripple sensitivity of a block that runs at a higher clock frequency thanthe blocks that are creating the supply ripple is reduced, in anembodiment in accordance with the present invention.

While the present invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the present invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the present invention without departing from its scope.Therefore, it is intended that the present invention not be limited tothe particular embodiment disclosed, but that the present invention willinclude all embodiments falling within the scope of the appended claims.

1. A clock multiplier circuit disposed on an integrated circuit devicehaving at least one other circuit comprising a plurality of logic gates,the clock multiplier circuit comprising: a delay line circuitfunctioning to produce at each of a plurality of outputs a delayedversion of a first clock signal, the delay of the delay line circuitbeing dependent upon at least one control signal and a supply voltage; acontrol circuit accepting as inputs at least two of the plurality ofoutputs of the delay line circuit, the control circuit producing the atleast one control signal, the control circuit adapted to adjust the atleast one control signal in order to maintain a predetermined phaserelationship of the at least two of the plurality of outputs of thedelay line circuit; and a mixer circuit adapted to combine a subset ofthe plurality of outputs of the delay line circuit in order to produce asecond clock signal having a number of cycles for each cycle of thefirst clock signal; and the clock multiplier circuit functioning toadjust a duration of one or more portions of the second clock signal inresponse to the supply voltage while producing the number of cycles ofthe second clock signal during each cycle of the first clock signal andmaintaining a predetermined timing relationship of the first and secondclock signals.
 2. The clock multiplier of claim 1 wherein the delay linecircuit has four outputs, each output being a version of the first clocksignal that is delayed by an amount of time equal to a multiple of onefourth the period of the first clock signal.
 3. The clock multiplier ofclaim 1 wherein the control circuit comprises: a phase detector circuitfor detecting a phase relationship between the at least two of theoutputs of the delay line circuit, the phase detector producing anoutput; and at least one filter for filtering the output of the phasedetector, the at least one filter producing the at least one controlsignal.
 4. The clock multiplier of claim 1 wherein the predeterminedphase relationship of the at least two of the plurality of outputs ofthe delay line circuit comprises a phase difference of 360 degrees. 5.The clock multiplier of claim 1 wherein the number of cycles of thesecond clock signal during each cycle of the first clock signal is aninteger value of at least two.
 6. The circuit of claim 1 wherein thedelay characteristics of the delay line circuit are adapted tosubstantially match the delay characteristics of the plurality of logicgates, with regard to changes in the supply voltage.
 7. A systemcomprising: at least one processor for processing data, the processorcomprising a plurality of logic gates; a memory communicatively coupledto the at least one processor; the at least one processor having a clockmultiplier circuit comprising: a delay line circuit functioning toproduce a plurality of signals, each signal being a delayed version of afirst clock signal, the amount of delay being dependent upon at leastone control signal and a supply voltage; a control circuit accepting asinputs at least two of the plurality of signals, the control circuitproducing the at least one control signal, the control circuit adaptedto maintain a predetermined phase relationship of the at least two ofthe plurality of signals by adjusting the at least one control signal; amixer circuit adapted to combine a subset of the plurality of signals inorder to produce a second clock signal having a number of cycles foreach cycle of the first clock signal; and the clock multiplier circuitfunctioning to adjust a duration of one or more portions of the secondclock signal in response to the supply voltage while producing thenumber of cycles of the second clock signal during each cycle of thefirst clock signal and maintaining a predetermined timing relationshipof the first and second clock signals.
 8. The system of claim 7 whereinthe control circuit comprises: a phase detector circuit for detecting aphase relationship between the at least two of the plurality of signals,the phase detector producing an output; and at least one filter forfiltering the output of the phase detector, the at least one filterproducing the at least one control signal.
 9. The system of claim 7wherein the predetermined phase relationship of the at least two of theplurality of signals comprises a phase difference of 360 degrees. 10.The system of claim 7 wherein the number of cycles of the second clocksignal during each cycle of the first clock signal is an integer valueof at least two.
 11. The system of claim 7 wherein the delaycharacteristics of the delay line circuit are adapted to substantiallymatch delay characteristics of the plurality of logic gates, with regardto changes in the supply voltage.
 12. A method of multiplying a firstclock signal to produce a second clock signal, the method comprising:receiving the first clock signal; delaying the first clock signal by aplurality of adjustable delays to produce a plurality of delayedsignals; determining a phase relationship of two of the plurality ofdelayed signals; modifying the plurality of adjustable delays based uponthe phase relationship and a supply voltage, if the phase relationshipdoes not meet a predetermined condition; refraining from modifying theplurality of adjustable delays based upon the phase relationship and thesupply voltage, if the phase relationship meets the predeterminedcondition; and generating a second clock signal using at least two ofthe plurality of delayed signals.
 13. The system of claim 12 whereineach of the delayed signals comprises a version of the first clocksignal that is delayed by an amount of time equal to an integer multipleof the period of the first clock signal divided by a predeterminedinteger.
 14. The system of claim 12 wherein the determining comprises:detecting the phase relationship of two of the plurality of delayedsignals to produce phase relationship information; and filtering thephase relationship information.
 15. The method of claim 12 wherein thepredetermined condition comprises a phase difference of 360 degrees. 16.The method of claim 12 wherein the number of cycles of the second clocksignal occurring during each cycle of the first clock signal is aninteger value of at least two.
 17. The method of claim 12 wherein atleast one of the delaying and modifying are adapted in order tosubstantially match the delay characteristics of the plurality ofadjustable delays to delay characteristics of a circuit receiving thesecond clock signal, with regard to changes in the supply voltage.18-23. (canceled)